The field of the invention relates to systems and methods for shared access between an embedded controller and a host processor to modules including but not limited to input/output modules. Embedded controllers are designed for specific tasks and/or to control a particular system, as part of a larger device or system. Embedded controllers perform functions such as system monitoring and control, verification of correct system operation (health monitoring), and/or troubleshooting and error recovery, handled when the host processor is off or malfunctioning or as a background fail safe operation when the host is active. As embedded controllers and host processors increasingly function together in controlling a computer environment, sharing access between embedded controllers and host processors to different elements of the computer environment becomes increasingly important.
There follows a brief description of prior art input/output modules. Input/output (“I/O”) modules allow the connection of peripheral devices to the computer (i.e., host processor and or embedded controller), typically through a bus interface. I/O modules commonly include one or more of the following: keyboard and mouse controller, floppy disk controller, serial ports, parallel ports, infrared ports, and general purpose input/output ports. It should be understood that the above list is not exhaustive and that I/O modules can include other modules which allow the connection of peripheral devices. The I/O modules are commonly but not necessarily integrated into one chip (i.e., an “input/output chip”) on the motherboard of a computer. However, other connection configurations of certain or all of the modules, for example, through a bus extension, are also possible. It should be evident that input/output chips include other modules in addition to input/output modules to improve the functionality of the chip including but not limited to: clock modules, power management modules, configuration, bus extensions, interfaces, reset circuitry, etc.
A representative prior art I/O chip 10 PC87364 “128-Pin LPC Super I/O with Extended Wake-Up and Protection Support” of National Semiconductor Corporation of Santa Clara, Calif., is shown in FIG. 1. Data sheets for chip 10 are available on the World Wide Web at www.national.com. Modules typical to input/output chips which are included in chip 10 are a serial port 12, an infrared port 14, a plurality of general purpose I/O ports (GPIO ports) 16, a floppy disk controller 18, a parallel port 20, a configuration module 24, a keyboard and mouse controller 30, an access bus interface 36 and a system wake-up control (SWC) 38. Other components particular to chip 10 include an interrupt serializer 28, a fan speed control and monitor 32, and a watchdog timer 34. Power sources VDD (main) 40, VSB (standby) 44, and VBAT (battery backup) 42 supply power to chip 10. Part of GPIO ports 16, and optionally part of SWC 38 are powered by VSB 44. VBAT 42 provides backup (using a battery) to critical events and configurations in SWC 38 and to other parts of chip 10, while VSB is off. All other components of chip 10 are powered by VDD 40. A host processor 26 is connected to an internal bus 54 through a low pin count (LPC) interface 22, allowing host processor 26 to access modules 12 to 22 and modules 28 to 38, and configuration 24. Modules 12 to 22 and modules 28 to 38 are collectively noted as a typical module 45 in FIG. 2.
Although the description below for FIG. 2 and FIG. 3 refer to components of chip 10 for illustrative purposes, the schemes shown in FIG. 2 and FIG. 3 are common to many prior art chips.
Prior art FIG. 2 shows a system 46 whereby host processor 26 accesses typical module 45 through an LPC interface 22 that converts an LPC bus to a data bus 56, an address bus 55, and a control bus 53. Typical module 45 is enabled based on the value of module enable bits 52 within registers in configuration 24.
To access particular module 45, host processor 26 sends the address 55 of a specific register 47 within particular module 45. Address 55 includes high bits which are compared by a comparator 49 with the base addresses+size 48 for each module 45 that are stored (i.e., configured) in configuration 24. The size provides a boundary on the highest possible address for each module 45, and the base address provides the lower boundary of addresses for each module 45. If no configuring process takes place, the base address of typical module 45 is retained at default value. As a result of the comparison, a module select (or as sometimes called “chip select”) 50 for particular module 45 is generated and placed on internal bus 54. Control signals 53 are converted to internal bus control 51 (i.e., in the format required by internal bus 54). In addition, address 55 includes lower bits which relate to the offset address. The offset address is specified with respect to the base address of particular module 45, and allows the identification of specific register 47 within particular module 45. The data 56 can then be read or written to specific register 47.
In certain modules 45, the approach to specific register 47 within particular module 45 is via a module-specific index register 59 (shown as optional in FIG. 2 using a broken line), and a module-specific data register 61 (also shown as optional in FIG. 2 using a broken line). Index register 59 and data register 61 are located at different offset addresses from the base address of module 45. For example, index register 59 can be located at offset zero (“0”) and data register 61 at offset one (“1”). In this case, two transactions are necessary to read or write. First, address 55 of index register 59 is sent along with data 56 to be written to index register 59 (in this case the data 56 is the index value of specific register 47). Next, address 55 of data register 61 is sent and data 56 can then be written to or read from specific register 47 via data register 61 (as is well known in the art, data register 61 is a “dummy register” and contains a duplicate of the contents of specific register 47). Note that if the index is already set to the correct value, there is no need to re-write the address prior to the successive data access operation.
Prior art FIG. 3 shows the mechanism for setting the configuration of typical module 45. Device configuration 24, includes a configuration index register 73, a configuration data register 74, global configuration registers 64 and a logical device number (LDN) configuration register 66. Index register 73 is located at address 2Eh or 4Eh of input/output address space 58, and data register 74 is located at address 2Fh or 4Fh of input/output space 60. Configuration registers related to typical module 45 include logical device specific configuration registers 70 organized in banks 69. Therefore, to access logical device specific configuration registers 70, two-dimensional indexing is required. In order for host processor 26 to access one of logical device specific configuration registers 70 relating to one of modules 45, one of banks 69 (i.e., logical devices 45) is selected by first specifying the index of LDN configuration register 66 in configuration index register 73, and then specifying the logical device number of one of modules 45 in configuration data register 74. Host processor 26 next chooses a logical device specific configuration register 71 by writing the index of configuration register 71 in configuration index register 73. The configuration data is then written to register 71 through configuration data register 74.
Note that in the above description of chip 10, there is no interface for an embedded controller and specifically no means for an embedded controller to access typical module 45 and configuration 24.
Prior art FIG. 4 shows a schematic 80 of the host bus interface of PC87570 (chip 82) of National Semiconductor Corporation of Santa Clara, Calif. Data sheets for chip 82, a keyboard and power management controller are available on the World Wide Web at www.national.com. Chip 82 includes an embedded controller core 84, which accesses a host bus interface 86 through a core bus 85 to ISA bridge 87. An external flash memory 81 is accessible by core 84 through a core bus 85 and a bus interface unit 89. When a host processor 98 asserts certain signals, host bus interface. 86 identifies the signals and requests control over core bus 85 using a core bus master mechanism (not shown in FIG. 4), thereby allowing host processor 98 to access flash memory 81 through host bus interface 86, core bus 85 and bus interface unit 89. The host transaction is extended using a ‘not ready’ indication (not shown in FIG. 4) until the transaction is completed.
After reset, core 84 in chip 82 needs to finish various system configurations and therefore blocks access of host processor 98 to shared memory 81. After core 84 has completed various system configurations, core 84 removes the access block and enables host processor 98 to access shared memory 81. Until the configurations are complete, if host processor 98 attempts access to shared memory 81, host processor 98 is indicated to wait using a ‘not-ready’ indication, or optionally a signal is sent to reset host processor 98. Note that no indication is given to core 84 if host processor 98 attempts access to shared memory 81 when shared memory 81 is blocked. Note also that the blocking of shared memory 81 occurs only during an initialization process.
A core and host arbitrator 88 arbitrates between host processor 98 and core 84 the access to the shared a Real Time Clock (RTC) module 100 on a resident device bus 91. A host access 96 to RTC module 100 and a core access 94 to RTC module 100 are illustrated by broken lines having an arrow at each end. RTC module 100 includes an index register RTCCA 102 and a data register RTCCD 104, which are used to access all internal registers 103 of all RTC banks 105. Index register 102 and data register 104 are located at consecutive addresses. Index register 102 holds the index of particular RTC register 103 that is read or written to through data register 104. Bank 105 is selected using the CRA register 101. In chip 82, both host processor 98 and core 84 can access registers 102 and 104.
Assuming that bank 105 has already been indicated through CRA register 101, host processor 98 accesses particular internal register 103, by sending the host address of index register 102 on a host bus 92 along with data. The address is translated into a chip select and address offset as explained with reference to FIG. 2. The data (which in this case is the index value of internal register 103) is then written to index register 102. Host processor 98 then sends the host address of data register 104. The data of particular register 103 can then be written or read through data register 104. Similarly, core 84 can access particular internal register 103 through index register 102 and data register 104. Core 84 sends the core address of index register 102 on core bus 85 along with the data. The data (in this case the index value of internal register 103) is then written to index register 102. Core 84 then sends the core address of data register 104. The data of register 103, which corresponds to the index value, can then be written or read through data register 104.
Note that although the core address sent by core 84 and the host address sent by host processor 98 may not be identical, two decoders (not shown in FIG. 4), one for core 84 and one for host processor 98 decode the two addresses to the same register.
A register CTS1 90 is accessed by core 84 and used to control host bus interface 86 with respect to RTC module 100 access.
CTS1 90 is shown in more detail in prior art FIG. 5. A lock RTC host access (LKRTCHA) 106 arbitrates the usage of RTC module 100 between host processor 98 and core 84. When LKRTCHA 106 is reset to zero (“0”), core 84 can not access registers 102 and 104 (and therefore can not access all internal registers 103), and only host 98 can access registers 102 and 104. When LKRTCHA 106 is set to one (“1”), host processor 98 can not access registers 102 and 104 (and therefore can not access all internal registers 103), and only core 84 can access registers 102 and 104. An RTC lock violation (RTCLV) 108 is set as an indication to core 84 if host processor 98 attempts to access RTC module 100 when LKRTCHA 106 is set to one (“1”). In parallel, the host access is completed in the following way: read access return a fixed value of zero and write access is completed ignoring the data written.
Other components of CTS1 90 will be mentioned only in passing. An RTC master reset (RTCMR) 107 when set to one (“1”), allows core 84 to access RTC protected memory. A host power on (HPWRON) 109 allows core 84 to monitor host power on, and a host master reset active (HMRA) 110 enables core 84 to monitor the status of a host master reset.
It should be noted that the RTC sharing scheme of chip 82 provides only an access block option, i.e., either core 84 or host processor 98 have exclusive control of RTC module 100. Chip 82 therefore allows shared access (exclusively one at a time) of host processor 98 and core 84 to RTC module 100. In order to prevent conflicts, host processor 98 and core 84 can not access RTC module 100 concurrently.
An example of a possible conflict that could occur if concurrent access were allowed to RTC module 100 (i.e., if access by one of core 84 or host processor 98 were not blocked) is the following scenario: Recall from the discussion with reference to FIG. 2 that (assuming bank 105 has already been selected) two additional transactions are necessary for either core 84 or host processor 98 to read to or write from internal register 103 because of the index/data registers. In a first host transaction, host processor 98 writes the index of internal register 103 to index register 102. Then, in a first controller transaction, embedded controller core 84 writes the index of another internal register 99 to index register 102. Finally, in a second host transaction, host processor 98 sends or receives data supposedly for internal register 103 which is instead written to or read from register 99 (because the index value of register 99 is in index register 102).
In addition, shared access is only implemented for one specific pre-defined input/output module (i.e., RTC 100 of chip 82) on resident device bus 91, even though chip 82 also includes other modules such as a keyboard controller, and a power management device. Also, there is no indication to host processor 98 when host processor 98 attempts to access RTC module 100 while LKRTCHA 106 is set to one (“1”). Only one indication is provided (RTC lock violation RTCLV 108) and only to embedded controller core 84.
Chip 82 is powered by a single voltage source (VCC). In addition, there is a battery backup for RTC module 100.
FIG. 6 shows another example of prior art sharing of input/output functions between an embedded controller 113 and a host processor 114. Chip 115 FDC37N972, is a product of Standard Microsystems Corporation (SMsC) headquartered at Hauppauge, N.Y. Data sheets of chip 115 can be found on the World Wide Web at www.smsc.com. Embedded controller 113 can disconnect access of host processor 114 to parallel port connector 116 by writing a bit 112 in a parallel port controls register of controller 113. A multiplexer 117 controlled by bit 112 selects either host processor 114 or embedded controller 113 for access to parallel port connector 116. Embedded controller 113 has no access to any other input/output functions. Chip 115 is powered by one of two voltage sources (VCC1, VCC2). Chip 115 includes two separate buses, one for host processor 114, and the other for controller 113, with each bus powered by a different voltage source.
W83627HF is an input/output chip developed by Winbond Electronics Corporation of Taiwan whose World Wide Web site www.winbond.com includes data sheets for W83627HF. In addition to the traditional I/O functions, W83627HF has integrated into it a hardware monitor 119. Refer to FIG. 7 which shows the access scheme to hardware monitor 119. The functions of hardware monitor 119 are controlled by a host processor 118 through an LPC bus 126. An embedded controller core 120 also controls hardware monitor 119 through I2C bus 122.
FIG. 8 shows the access scheme through LPC bus 126. A hardware monitor index register 128 includes a bit 130 which is set to one (“1”) by a write to index register 128. Bit 130 is cleared by a read or write from/to a data register 129. Bit 130 can be seen from both LPC bus 126 and I2C bus 122. Bit 130 should be checked prior to beginning an LPC bus 126 or I2C bus 122 transaction (see FIG. 7). For the scheme to work, either host processor 118 or embedded controller core 120 must perform the following sequence prior to any data access (read or write), without exception even for successive data accesses (i.e., the index even for successive data accesses must be rewritten each time). A read or write starts by reading index register 128 and checking that bit 130 is clear. If bit 130 is not clear, the operation is repeated until bit 130 is clear. Once bit 130 is found to be clear, the desired index is written to index register 128. Index register 128 and bit 130 are both read to check that the address is right and bit 130 is set. If bit 130 is not set, the process starts at the beginning. If bit 130 is set, one data item may be read or written from/to data register 129. Even using the above scheme, the mechanism will fail if both host processor 118 and embedded controller core 120 try to read and/or write locations with the same index value.
There is a need in the art for systems and methods for allowing shared access by an embedded controller and a host processor to modules both internal to chips and off bus extensions, including but not limited to modules within input/output (“I/O”) chips or accessible through bus extensions off input/output chips. There is also a need in the art for systems and methods for allowing shared access by an embedded controller and a host processor to more than one module. There is also a need in the art for systems and methods for allowing concurrent access to certain modules by an embedded controller and a host processor. There is also a need in the art for a protocol which allows access by an embedded controller to more than one module.